PL  |  NL  |  FR  |  ES  |  PT  |  IT  |  DE  |  DK  |  NO  |  SE  |  FI  |  GR  |  JP  |  CN  |  KR  |  RU  |  AE

  Report this article

More information

BIOS Functions

Flash BIOS

PCMCIA

Port forwarding is not just for router

What is a Computer Bus

PCI Signal Groups

Memory Hierarchy

Address Lines and Buses

Power6 Processor: World`s Fastest Processor

How to install a motherboard

Tips you should know before choosing a motherboard

Memory Ranges

Tips on how to choose a processor

Troubleshooting Memory Installation and Operation

How to install Socket 5 and Socket 7 processors

Because most of the PC industry viewed IBM's licensing and marketing of Micro Channel as essentially absurd, a rival naturally arose, Extended Industry Standard Architecture. The EISA committee that crafted the standard was both motivated and constrained by conflicting design goals. They strove to create a 32-bit expansion standard for PCs that incorporated as many of the innovations of Micro Channel as possible without infringing on IBM's intellectual property rights in Micro Channel's technologies (so no licensing fees would be due). While pushing up performance, they wanted to maintain backward compatibility with the huge installed base of ISA expansion boards.

By necessity, these lofty goals were amended. The touted backward compatibility was incomplete: ISA boards work in EISA but not vice versa, and adding an ISA board to an EISA system disables part of the EISA system's capabilities (for example, the capability to share an interrupt). Moreover, EISA was unable to escape the need to license technology from IBM. After all, IBM owns basic patents on technologies required to build any PC no matter whether Micro Channel ideas are included.

Despite the diminished expectations, however, the resulting EISA specification has become the basis of many high performance computers. It works effectively. Although it, like Micro Channel, has failed to be a major force in the PC mainstream, the reasons relate to applications and cost rather than technical capability (again, like Micro Channel). Although EISA shows some promise for the next generation of PCs, it will likely be eclipsed by newer designs like PCI.

Physical Characteristics. At the heart of the EISA specification was its highly promoted backward compatibility with ISA. Under EISA, all existing PC expansion boards are plug-compatible (at least to some extent) with newer, high performance EISA computers, although the opposite is not true and some exceptions do exist. To achieve this required some big compromises-for example, retaining the 8 MHz bus speed limit. In addition, it demanded an entirely new kind of connector and unprecedented cooperation in a competitive industry.

The physical specifications between the old and new standards are remarkably similar. EISA expansion boards are the same size and shape as AT boards, with the standard setting the maximum (at 13.4 inches long and 4.5 inches high, from the top of the board to its bottom edge), with smaller boards such as so-called short cards, still accepted. But EISA makes some specific changes aimed at ensuring future products are even more inter-compatible than PC boards are today.

A seemingly minor change holds the potential for making a big difference. All measurements for EISA boards are specified from a common origin-that is, you measure all dimensions from a common starting point. For EISA, that point is the center of the expansion connector rather than an edge of the card. As a result, tolerances are smallest and the fit of boards is best where it counts most, at the expansion connector. EISA boards should fit better than their predecessors.

Another EISA change may have greater implications for existing PC expansion boards. While EISA accepts all physical configurations of current expansion boards, it prohibits from future products the addition of skirts-except for a mini-skirt located between the expansion connector and card-retaining bracket.

The centerpiece of the EISA specification is its expansion connector, the design of which ensures backward compatibility with PC-bus cards while allowing full 32-bit expandability of EISA peripherals. It adds 90 new connections (55 new signals) without increasing the size of the connector itself and accepts both EISA and classic-bus boards indiscriminately.

The clever, two-tier design of the connector actually represents a revision on the original EISA concept. The EISA connector originally announced in 1988 relied on what was in effect two parallel connectors-one that provided the compatible link-up with existing expansion boards and a second connector, offset from the expansion board, for 32-bit data transfers and addressing. The parallel-connector design was criticized for various deficiencies including its need for inordinately high insertion force (the effort required to plug a board into a slot). Such effort was believed to be required to squeeze a board into this connector that it nearly precluded the use of cost-saving automatic insertion machinery in the building of new computers.

Because the new EISA connector is physically the same size as a traditional expansion connector, it requires about the same insertion force-35 pounds-versus the 100-plus estimated for the proposed parallel connector. It should cause no problems for automatic insertion machinery.

The new connector achieves its combination of compatibility and full 32-bit expandability by branching out vertically instead of horizontally. In the new EISA connector, the contacts for enhanced functions are built into a second, lower level. Existing PC expansion boards can be inserted only about halfway into EISA slots to engage only the PC bus contacts. Five keys-plastic stops molded into the EISA connector-prevent older boards from going farther in. EISA boards have cut-outs that fit into the keys and allow the boards to be fully inserted into the connector. This keying prevents old-bus cards from shorting out the EISA connections, which holds the potential of damaging the EISA computer. When the card is fully inserted, both the upper and lower sets of contacts engage pads on the EISA board.

Because of its need for this deeper insertion, the edge connector on an EISA board is consequently a bit longer (about 0.2 inch) than that of a classic bus board.

Nothing stops EISA boards from fitting into ordinary 16-bit AT expansion slots, however. In fact, because of the odd arrangement of contacts on EISA boards, inadvertently inserting an EISA board into a old AT connector can potentially send signals into the wrong circuits-not enough fireworks to give Mr. Scott apoplexy, but sufficient to render the host system dysfunctional. Consequently, EISA boards should never be inserted into non-EISA computers even though they physically can fit the slots.

EISA also strives to maintain compatibility with the power demands of old-bus expansion boards. Under the EISA specification, a generous availability of power is assumed for each expansion slot, freeing peripheral designers from the need to use special low power components. Over 45 watts at four different voltages are available to each EISA expansion slot.

Of course, such availability takes an optimistic view of the total reserves of the system power supply. Filling the eight slots envisioned in a complete EISA system with hungry expansion boards would require over 325 watts. Even without considering the needs of mass storage devices and the system board itself, a fully-expanded EISA computer would require a huge power supply. Then again, nothing about the EISA design implies expansion boards require any more power than old-bus cards, so traditional power levels likely are adequate.

Enhanced Industry Standard Architecture Bus Pinout

The original impetus behind the search for a new bus standard was the 16-bit classic AT bus' incapability to deal with the 32-bit needs of the newer Intel microprocessors (specifically, the 386DX and 486). The first step in wringing full performance from these chips is to move data around in the largest blocks they can manipulate in a single operation, specifically 32-bit double-words. Widening the data path to 32-bits in itself can double the speed of data transfers in an AT-style computer, all else being equal (which it definitely is not in the case of EISA). To gain this instant advantage over the classic bus, EISA adds 16 new data lines to the pinout of the EISA connector.

The classic AT bus imposes another limit on higher powered microprocessors. Its 24 address lines enforce a maximum size of 16 megabytes on directly-addressable memory (as opposed to bank-switched memory, like that available under the EMS standard). To accommodate the complete addressing capabilities of the 32-bit Intel microprocessors-four gigabytes-EISA also broadens the address bus to a full 32-bits. The new address lines are labeled with the prefix LA in the pinout.

Note that EISA's endowment is more generous than a mere eight additional address lines. The standard also adds new lines for indicating some of the lower-order address bits, to some extent duplicating the function of the classic bus but with an important change. The EISA lower-order address lines (LA2 through LA16) are latching; that is, they provide stable signals through the address cycle instead of just at its beginning. Note that the EISA address extensions (the upper eight bits) to the classic bus also latch. Unlike Micro Channel, EISA permitted full DMA reach to all four gigabytes of memory addresses from its inception.

Sometimes all 32-bits of the data bus are not needed in a data transfer. For example, a program may need only to move a byte from one memory location to another. EISA provides four new signals to indicate which bytes of the double-word of data on the bus are significant-the Byte Enable signals BE0 through BE4.

To maintain compatibility with as many classic bus expansion boards as possible, EISA is designed to accommodate devices that have either 8-, 16-, or 32-bit interfaces. This diversity requires some method of preventing a device from trying to dump 32 bits of data to another that has only a 16-bit interface (in which case half the data would be lost).

EISA provides two signals to indicate what size data transfers a device can handle. To indicate that it has access to the full 32-bits of the EISA bus, a device sends the EX32 signal. Similarly, the EX16 signal indicates that a device only supports 16-bit transfers. If neither signal is present, the system must assume that the particular device can handle only eight-bits of data at a time. (These signals supplement those on the classic bus that indicate 8- or 16-bit transfer width.)

EISA doesn't stop with bus-width signaling. The standard also provides for the automatic translation of the width of bus signals, for instance breaking down the 32-bit signal of an EISA card into four sequential eight-bit signals that can be digested by old classic bus expansion boards. A special integrated circuit, the EISA Bus Controller, moves data into the appropriate byte lanes and translates the control signals on the bus accordingly.

Advanced Transfer Modes. EISA goes well beyond simply providing extra signals to add new data and addressing capacity to the classic bus. Other EISA enhancements also require new signals to be assigned to bus connections. These signals include support for burst-mode data transfers (MBURST and SLBURTS), new timing signals to help manage fast data transfers (START and CMD), even a signal to slow down the bus with wait states (EXRDY).

Under EISA, all the other signals on the classic bus retain their former definitions and functions to maintain backward compatibility with older expansion boards. The big challenge faced by the EISA engineers was to fit all these signals on a connector that would still allow the use of old expansion boards.

Compatibility is also among the most formidable problems in squeezing more raw speed-more megahertz-from the AT bus. Simply upping the clock speed that synchronizes data transfers across the bus is out of the question because any speed increase can cause conniptions for existing expansion boards. Many classic bus boards cannot operate at bus speeds much higher than the eight megahertz used in the AT or ten megahertz used by some compatibles.

To help ensure compatibility, EISA does not increase the raw speed of the clock driving the expansion bus. The specification calls for a bus clock (BCLK) oscillating at a fixed rate between 6 and 8.33 megahertz, the latter figure being one-quarter the 33 MHz clock speed of today's fastest microprocessors.

The bus speed is a submultiple of the system clock frequency because the EISA is nominally a synchronous bus-it operates in lock-step with the host microprocessor-but not necessarily. Bus masters can take over control and alter some aspects of system timing to achieve higher data throughputs.

Such altered timings are necessary because the bus speed limit is more severe than the megahertz would imply. The actual data transfer rate of ISA is limited by its two-cycle per transfer limitation with the bus going through an elaborate hierarchy of commands for every byte that's transferred. Although EISA allows this data transfer method, it also adds two faster schemes of its own: compressed transfers and burst mode. Compressed transfers are 50 percent faster in that data can be moved every one and a half bus cycles. Burst mode moves data every cycle, resulting in an effective transfer rate of 33 megabytes per second (8.33 MHz bus speed and 32-bit data path).

The key to EISA's compressed cycle operation is a special timing signal (CMD), which serves as a supplement to the bus clock. During compressed transfers, the CMD signal operates at twice the speed of the bus clock, and the data transfer is required to take place during its duration.

In burst mode, the addresses for data transfer are asserted at the beginning (for writing data) or the end (for reading data) of every clock cycle. The data is actually put on the bus one-half or one and a half cycles later, locked to CMD.

The EISA burst data mode has advantages as well as limitations. EISA burst mode can move noncontiguous data because an address is given with each transfer. However, EISA allows only the least significant ten address bits to change during a burst cycle, effectively limiting a burst data to addresses within a block of 1,024 double-words in memory. In addition, EISA does not permit reads and writes to be mixed in a single burst because of the differences in the timing of these signals.

Don't confuse the fast 33 megabyte per second maximum data transfer rate with the even faster 33 megahertz operation of some once-regarded-as-fast PCs. While both the EISA bus and the system memory of these computers is 32 bits wide, the maximum EISA bus clock speed remains 8.33 MHz, effectively one-quarter the speed of system board memory. In other words, in EISA computers slotted memory is still slower than system board memory, just as it is in classic bus machines. High performance (which, for practical purposes, means all) EISA computers still are built with proprietary memory expansion slots that operate at the full speed of the system (not the bus) clock.

DMA Modes. If any one part of the old AT needed improvement, it was its Direct Memory Access system. While DMA controllers have the potential for speeding system operation, PCs and ATs failed to deliver on that promise. DMA transfers on these systems can be painfully slow-so slow that DMA was abandoned for hard disk transfers in the AT.

On an AT, for example, DMA transfers ordinarily take place at the agonizing rate of one megabyte per second. Although a speed of two megabytes per second is theoretically possible using the three 16-bit DMA channels in the AT, DOS is limited to eight bit transfers and, thus, the lower rate.

New DMA timings and techniques show some of the most creative aspects of the EISA design. Besides AT-compatible DMA transfers, EISA adds three new types-Types A, B, and C (the last also known as Burst DMA)-all three of which can make 8-, 16-, or 32-bit transfers. In addition, multiple transfers also can be chained to send the same bytes to different locations. Under EISA, a maximum DMA data transfer rate of 33 megabytes per second is available with 32-bit transfers in burst mode.

The default DMA timing is the slowest mode, AT-compatible eight-bit transfers. The EISA specification envisions the other modes being brought to life with software drivers. With the proper drivers, most classic bus expansion board can take advantage of Type A transfers; a few also can take advantage of double-speed Type B transfers. EISA boards are required to use Type C or 32-bit transfers of any type.

Each type of DMA brings an improvement in data transfer rate. For a given width of data path, Type A transfers are about 30 percent faster than AT-style DMA. Type B transfers double the AT speed. Type C transfers are more than four times faster than AT transfers.

For the most part, these speed increases are made simply by specifying different data transfer protocols that involve fewer bus cycles in each DMA move. In the AT environment, each DMA move (8- or 16-bit) requires eight bus cycles, during most of which nothing is really happening. Type A transfers merely trim two of the wasted bus cycles from each DMA move. Type B transfers are more extreme, cutting the number of cycles per DMA move to four. Because newer expansion boards can operate at higher rates, many classic bus expansion cards can operate at these speeds.

Under the EISA specification, Type C DMA transfers compress all the necessary signal manipulations into a single bus cycle, with specific signal transitions occurring at the leading and trailing edges of the bus clock. Only EISA expansion cards are capable of this transfer method, and even they have their limitations. Only the ten lowest-order bits of the address bus are allowed change within the confines of this tight timing, with the result that Burst Mode DMA transfers on EISA are limited to addresses within a single 1,024-byte page.

In addition to creating new, high speed transfer modes, the EISA specification also expands the reach of DMA. Because of addressing limitations, classic bus systems could provide DMA transfers only through the lowest 16 megabytes of memory addresses. EISA allows DMA transfers anywhere within a four gigabyte range of physical memory.

The rate at which data can move during a DMA transfer depends on how many bits are moved at a time. All seven EISA DMA channels support up to 32-bits; the channels differ only in priority. The higher-numbered channels (5, 6, and 7) are serviced more often when an EISA system is heavily loaded.

Bus Mastering. The most significant borrowing that EISA makes from Micro Channel is bus mastering. In EISA systems, both the operation and nomenclature differ from the IBM design-not just for the sake of originality but also because IBM's designs are protected by patents and other intellectual property rights. In an EISA system, the arbitration control element is called the Integrated System Peripheral chip (and, strangely, not the EISA Bus Controller). The ISP acts just like the Micro Channel Central Arbitration Point and determines which system function gets control of the expansion bus.

Every arbitration system has rules. Mom, confronted with caring for a crowd of kids from the neighborhood may, for example, let the kid that screams the loudest go first in line just to get some peace and quiet. EISA has a much more pragmatic, more deterministic set of rules for priority. Control rotates through three classes: memory refreshing, DMA transfers, and a combination of the microprocessor and bus masters. In every control cycle, each element receives control in turn. If, however, several DMA channels request bus control, only one gets it per control cycle. In effect, control is like a menu in an old-fashioned Chinese restaurant-in each arbitration cycle, the system selects one from column A, memory refreshing; one from column B, DMA; and one from column C, the bus masters/microprocessor.

Which of the six EISA DMA channels gets control rotates through the circle of those needing it until DMA channels all are served. Actually, this rotation is a pair of cycles, wheels within wheels. Three high priority DMA channels (corresponding to the 16-bit channels in an AT system but allowed any transfer width under the EISA specification) going through one rotation and three lower priority channels in another rotation. One low priority channel gets control for each complete cycle of three high priority channels.

The microprocessor and bus masters form another wheel-within-wheel arrangement. Each time the microprocessor/bus master column is selected, either the microprocessor or bus master gets control, whichever was not selected on the last cycle. In other words, the microprocessor is served half the time; the bus masters the other half. Another cycle selects which of the various bus masters gets served when the bus master selection pops up.

Consequently, memory refreshing is assigned the highest priority in an EISA system. Every arbitration cycle includes memory refresh. That's as it should be because without memory refreshing, the system would crash. DMA transfers are next highest in that one active DMA channel would get attention every cycle. The microprocessor has the next highest level of priority, getting control at least every other cycle. At best, any given bus master can only match the priority level of the microprocessor. If several are active, each gets control only after a delay of many arbitration cycles.

Considering the complexity of this arbitration hierarchy, the hardware that brings it to life is actually simple. Only two slot-specific signals are necessary for each expansion board. The controlling logic is all contained inside the ISP chip, so the designers of expansion boards need not worry about complex decision-making circuitry.

When a bus master board wants to request bus access, it only needs to assert its Memory Request (abbreviated MREQx, where x is the slot number, in EISA nomenclature) line. The ISP informs the bus master that it can take control of the bus by asserting the Memory Acknowledge (or MAKx) signal associated with the slot in which the bus master is located.

The EISA standard also allows a form of bus master to be built solely using the AT bus. Such cards use the DMA signals to control the bus, the DMA Request (DRQ) line indicating a need to use the bus. Permission is sent back to the board on the associated DMA Acknowledge line (DAK).

Because these classic bus masters don't have access to all the EISA timing signals, they hold the potential for overstaying their welcome, getting so involved in a transfer so as to not yield control to the one function that absolutely must have it-memory refresh. Consequently, the EISA design requires these boards to have built-in timing circuits to limit the duration of their bus access.

Interrupt Sharing. Speed and data connections are not the only things in short supply in classic bus systems. System interrupts amount to a paltry few once even a modest number of expansion boards are plugged in. Nearly every device connected to the input/output channel-from hard disks to serial ports to video controllers-demands at least one interrupt for optimum performance.

Seven additional interrupts were added to the AT system design when the eight of the original PC proved too few. EISA could have done likewise and dosed new systems with new interrupt channels, but that strategy becomes overly complex and expensive as the number of interrupts increases.

The more moderate solution is to share interrupts between peripherals. With sharing, the 15 existing interrupts could potentially serve needs of an EISA system no matter how much it might be expanded.

Maintaining classic bus compatibility and implementing interrupt sharing is a technological nightmare, however. The principal reason for this problem are the edge-triggered interrupts used by the AT bus. Level-sensitive interrupts are, of course, inherently less susceptible to noise and confusion. But using level-triggered interrupts in the PC environment is problematic. Getting level-sensitive interrupts to work with software that uses edge-triggered interrupts is one difficulty. Maintaining compatibility with existing edge-triggered boards is another, particularly considering that the two kinds of interrupts won't work together on a given interrupt control line. To maintain full backward compatibility, however, EISA must be able to mix the two types of interrupts without causing additional problems.

The EISA approach is to make each interrupt individually programmable between edge-triggered and level-sensitive operation. Old boards can use the edge-triggered interrupts they prefer, one board per interrupt. New EISA expansion boards can share the other interrupts programmed to be level-sensitive.

The one remaining obstacle with this system is that level-sensitive interrupts require a different kind of hardware than does the edge-triggered variety. Because of this difference, plugging a board designed to use an edge-triggered interrupt effectively blocks the use of that interrupt by level-sensitive boards.

This difference in technology also holds the potential for damaging the hardware involved in the conflict. Thankfully, the EISA design minimizes this danger by specifying the inclusion of a current-limiting resistor in the interrupt lines of level-sensitive EISA boards. Nevertheless, EISA supports interrupt sharing only on EISA boards. Existing classic bus expansion cards cannot share interrupts with each other or EISA cards.

Software Setup. At minimum, setting up all the technical wizardry that EISA's engineers have conjured into a system might seem to require a magic wand-what with addressing and interrupt considerations, not to mention four DMA types, the data transfer modes, and the rest of the EISA variables. Even without the innovations, setting up an expansion board meant for the classic bus is generally an exercise in frustration that requires the careful matching of DIP switch and jumper settings with the needs of the board and the available interrupts and memory in the host system. Make one mistake-which is almost assured owing to the deplorable state of most documentation-and the host system likely cannot even boot, let alone diagnose the problem. Fortunately, EISA incorporates several strategies to alleviate these setup problems.

The EISA design automatically prevents conflicts in the assignment of some system resources. In addition, it incorporates a software-mediated setup procedure that finds, flags, and even corrects conflicts to the extent of automatically configuring the system. If that's not enough versatility, EISA also allows old-fashioned switch and jumper configuring of boards as well.

One inspired aspect of EISA automatically eliminates the conflict of input/output port assignments. In classic-bus computers, expansion boards can choose from any ports in the range 100(Hex) to 3FF(Hex) for their needs. You have the job of assigning ports from a range within the range that the board-maker had selected to use. You also have the responsibility of detecting and resolving conflicting port assignments.

In contrast, the EISA design assigns a unique range of ports to each expansion slot. Boards are still confined to a limited range of three-digit hexadecimal addresses, but each expansion slot adds an extra digit to distinguish the ports used by its associated board from those in the other slots. This scheme makes it physically impossible for two boards to try to use the same I/O port addresses.

Each board also can be individually addressed to ferret out information stored in common locations. Besides the slot-specific signals for managing bus arbitration (MREQx and MAKx), each EISA slot incorporates one additional slot-specific signal that redefines a signal assignment on the classic bus, now called AENx. It enables each expansion board to respond independently of the others so that each board can be individually addressed and controlled. By selectively activating the AENx bus line for each slot, the host EISA system can query individual boards, isolate them, or simply identify them.

The nomenclature of these slot-specific signals alone limits EISA to its avowed maximum of 15 expansion slots per system (the x in the signal names is replaced by the hexadecimal designation of the slot), although the specification states that systems with more than eight slots are unlikely.

Each make and model of EISA expansion board is assigned a unique EISA Product Identifier, which is stored on the board at input/output port addresses 0xC80(Hex) to 0xC83(Hex). The first two bytes store, in compressed form, a three-letter abbreviation identifying the board manufacturer (the characters "ISA" reserved to indicate generic classic-bus boards). The next byte encodes a two-digit product number, and the final byte encodes a two-digit revision number. The manufacturer's abbreviation is assigned by BCPR Services, the organization that distributes the EISA specification. Manufacturers create their own product and revision numbers. System boards are assigned identification numbers using a similar scheme.

Supplementing this slot- and card-identification arrangement is an automated setup system. Through a standardized setup program, you can allocate the resources of your EISA system resources or let the system automatically set itself up.

This system brings together several diverse elements. Setup information is maintained in a hardware extension to the CMOS configuration memory used by AT-class computers. Additional battery-backed-up CMOS memory is assigned to remembering the essential parameters of the board installed in each expansion slot.

To load this information into memory, each EISA system manufacturer provides a setup program, either on disk or in ROM. This program integrates with each product that requires setup through Configuration Files, disk-based database records holding setup information in a standardized format set by the EISA specification. The setup program reads the disk-based data to customize itself for the setup needs of each specific product installed in the computer host.

The product identification numbers are used as a key. Stored in CMOS memory, they are used to look up Configuration Files each time the system is switched on. This system centralizes the non-volatile memory needed for memorizing the setup of each board, eliminating the expense of incorporating such memory into each expansion product.

Even the interface of the setup program has been standardized across EISA machines so that if you can set up one, you know how to configure them all. If you don't, mastering the procedure is easy-you only need to pull down menus to choose the options you want.