VGA Modes

Even in the early 1980s, a frame buffer of 32K proved inadequate. To allow for more space in the frame buffer, IBM developed a paged frame buffer for its EGA system. This same memory arrangement is used today for the VGA system upon which all current video boards are based.

In moving to paged memory, IBM also moved the frame buffer to its current location at a base address of 0A0000(Hex), the very bottom of High DOS memory. Normally, the full expanse of the system's display memory is split four ways into 64K banks, although a two way 128k bank split is also possible. The latter mode extends across the ranges used by the old monochrome and low resolution color frame buffers.

A register, called the Map Mask Register, that is part of the VGA chip, controls which banks the system microprocessor addresses through a 64K range of high memory addresses. The VGA specification puts the Map Mask Register at I/O port 03C5(Hex). Several registers actually share this port address to economize on port usage. The VGA Sequencer Register at port address 03C4(Hex) controls the function of the port used by the Map Mask Register. When the Sequencer Register is set to the value 02(Hex), port 03C5(Hex) gives access to the Map Mask Register.

The Map Mask Register has four control bits. In the VGA's original 16-color mode, each bit nominally controls a bit plane and switches the intensity on or off red, green, and blue signals (listed from most significant bit to least). Unlike most bank switching systems, the VGA system allows multiple banks to be switched on simultaneously. This scheme allows an onscreen hue that's mixed from more than one color to be loaded in a single cycle. For example, if your system could only activate the VGA banks individually, writing a bright white dot would take four separate operations-writing a bit of one color, switching banks, then writing another color, and so on. By activating all four banks simultaneously, writing the white bit takes only one switch and write operation.

Addressing within each bank is linear in the original 16-color VGA graphic mode. That is, the memory arrangement puts onscreen pixels and lines into memory in the same order that they appear on the screen. The bit data in a byte from most significant to least significant bit corresponds to an onscreen sequence of eight pixels in a line from left to right.

In 256-color mode, each byte of memory defines the color of a single pixel. The bank control logic of the VGA system divides the 256K of memory for onscreen pixels into four 64K blocks. These banks essentially duplicate one another but provide a convenient way of scanning color plane data into the RAMDAC. Because there are eight color signals per pixel and the VGA system is designed to scan four color planes at a time, the 256-color pages are scanned twice to make the transfer.

In text modes, the VGA memory banks act as if they are at the old mode locations and are similarly interleaved: odd bytes of display memory in the first bank; even bytes in the second bank. In normal text mode operation, this corresponds to putting the character values in the first bank and attribute data in the second bank. The various pages of character memory start at each 2K paragraph address boundary. For example, when operating in color text mode, the first page will be based at 0B8000(Hex), the second page at 0B8800(Hex), and so on.

The mechanics of the address remapping used by the VGA system are relatively straightforward. A register in the VGA control circuitry acts as the switch. The Memory Map Register controls the base address of the VGA's video memory and the page size of each bank.

Accessing the Memory Map Register is a two step process. First the Graphic Address Register at microprocessor I/O port must be set with a value of 06(Hex) to enable writing to the Memory Map Register through the VGA's Miscellaneous Register at microprocessor port address 03C2(hex), an address shared with a number of other functions. Bits 2 and 3 in the Memory Map Register control bank address and size.

Setting Bit 3 of the Memory Map Register to zero locates the base address of the frame buffer at 0A0000(Hex). Bit 2 then controls bank size. Set to zero, it specifies two 128K banks; set to one it indicates four 64K banks.

When Bit 3 of the Memory Map Register is set to one, bank size is set at 32K, and Bit 2 controls the base address used by the two permitted banks. With Bit 2 set to zero, the buffer base address is 0B0000(Hex); when set to one, the buffer base address is 0B8000(Hex).