RISC

Although long the mainstream of computer and microprocessor design, microcode is not necessary. While system architects were staying up nights concocting ever more powerful and obscure instructions, a counter force was gathering. Starting in the 1970s, the microcode approach came under attack by researchers who claimed it takes a greater toll on performance than its benefits justify.

By eliminating microcode, this design camp believed, simpler instructions could be executed at speeds so much higher that no degree of instruction complexity could compensate. By necessity, such hard-wired machines would offer only a few instructions because the complexity of their hard-wired circuitry would increase dramatically with every additional instruction added. Practical designs are best made with small instruction sets.

John Cocke at IBM's Yorktown Research Laboratory analyzed the usage of instructions by computers and discovered that most of the work done by computers involves relatively few instructions. Given a computer with a set of 200 instructions, for example, two-thirds of its processing involves using as few as 10 of the total instructions. Cocke went on to design a computer that was based on a few instructions that could be executed quickly. He is credited with inventing the Reduced Instruction Set Computer or RISC in 1974. In 1987 Cocke's work on RISC won him the Turing Award (named for computer pioneer Alan M. Turing, known best for the Turing Test definition of artificial intelligence), given by the Association for Computing Machinery as its highest honor for technical contributions to computing.

Note that the RISC concept pre-dated the term, however. The term RISC is credited to David Peterson, who used it in a course in microprocessor design at the University of California at Berkeley in 1980. The first chip to bear the label and to take advantage of Cocke's discoveries was RISC-I, a laboratory design that was completed in 1982. To distinguish this new design approach from traditional microprocessors, microcode-based systems with large instruction sets have come to be known as Complex Instruction Set Computers or CISC designs.

Cocke's research showed that most of the computing was done by basic instructions, not by the more powerful, complex, and specialized instructions. Further research at Berkeley and Stanford Universities demonstrated that there were even instances in which a sequence of simple instructions could perform a complex task faster than a single complex instruction could. The result of this research is often summarized as the 80/20 Rule: about 20 percent of a computer's instructions do about 80 percent of the work. The aim of the RISC design is to optimize a computer's performance for that 20 percent of instructions, speeding up their execution as much as possible. The remaining 80 percent of the commands could be duplicated, when necessary, by combinations of the quick 20 percent. Analysis and practical experience has shown that the 20 percent could be made so much faster that the overhead required to emulate the remaining 80 percent was no handicap at all.

In 1979 IBM introduced its model 801, the first machine to take advantage of Cocke's findings. It is credited as the first computer intentionally designed with a reduced instruction set. The 801 was a 32-bit minicomputer with 32 registers that could execute its simple instructions in a single processor cycle. The 801 led to the development of IBM's Personal Computer/RT in 1986, which was refined into the RISC System/6000. The multi-chip processor in the RS/6000 was consolidated into a single chip that formed the basis of IBM's PowerPC microprocessors (now being jointly developed with Motorola).

The Berkeley line of RISC research led to the RISC-II microprocessor (in 1984) and SOAR. Together, these laboratory designs inspired Sun Microsystems to develop the SPARC line of microprocessors.

RISC philosophy also inspired John Hennesey at Stanford University to found the MIPS project there. Although the MIPS group once said that the acronym was derived from a description of their design goal (Microprocessor without Interlocked Pipeline Stages), more commonly it is held to stand for Millions of Instructions Per Second, a rudimentary yardstick of microprocessor performance. The MIPS project eventually spawned RISC-chip developer MIPS Computer Systems (known as MIPS Technologies since its merger with Silicon Graphics in 1992). The Silicon Graphics R2000, R3000, R4000, R4400, and R6000 chips trace their heritage back to the Stanford line of development.

No sharp edge demarcates the boundaries of what constitutes a reduced or complex instruction set. The DEC Alpha, for example, one of the most recent RISC designs, has a very full repertoire of 160 instructions. In contrast, Intel's Pentium, generally considered to be a CISC microprocessor, features about 150 instructions (depending on how you count). In light of such incongruities, some RISC developers now contend the RISC term has stood for, not Reduced Instruction Set, but rather, Restricted Instruction Set Computer all along.

More important than the nomenclature or number of instructions that a computer or microprocessor understands in characterizing RISC and CISC is how those instructions are realized. Slimming down a computer's instruction set is just one way that engineers go about streamlining its processing. As the instructions are trimmed, all the ragged edges that interfere with its performance are trimmed off, and all that remains is honed and smoothed to offer the least possible resistance to the passage of data. Consequently, RISC designs are best distinguished from CISC not by a single "to be or not to be" rule but whether (and how well) they incorporate a number of characteristics. Some of the important characteristics of RISC include:

• Single-cycle or better execution of instructions. Most instructions on a RISC computer will be carried out in a single clock cycle, if not faster, because of pipelining. The chip doesn't process a single instruction in a fraction of a cycle, but instead works on multiple instructions simultaneously as they move down the pipeline. For example, a chip may work on four instructions simultaneously, each of which requires three cycles to execute. The net result is that the chip would require three fourths of a clock cycle for each instruction.

• Uniformity of instructions. The RISC pipeline operates best if all instructions are the same length (number of bits), require the same syntax, and execute in the same number of cycles. Most RISC systems have instruction sets made up solely of 32-bit commands. In contrast, the CISC command set used by the Intel-standard microprocessors in PCs uses instructions that are eight, sixteen, or thirty-two bits long.

• Lack of microcode. RISC computers either entirely lack microcode or have very little of it, relying instead on hard-wired logic. Operations handled by microcode in CISC microprocessors require sequences of simple RISC instructions. Note that if these complex operations are performed repeatedly, the series of RISC instructions will lodge in the high speed memory cache of the microprocessor. The cache contents then act like microcode that's automatically customized for the running program.

• Load-store design. Accessing memory during the execution of an instruction often imposes delays because RAM cannot be accessed as quickly as the microprocessor runs. Consequently, most RISC machines lack immediate instructions (those that work on data in memory rather than in registers) and minimize the number of instructions that affect memory. Data must be explicitly loaded into a register using a separate load instruction before it can be worked on. The sequence of instructions in program code can then be organized (by an optimizing compiler) so that the delay on the pipeline is minimized.

• The hard work is in the software. The RISC design shifts much of the work in achieving top performance to the software that runs on the system. RISC performance depends on how efficiently the instructions for running the system are arranged. Processing multiple instructions in a single clock cycle requires that the program pipeline be kept full of instructions that are constantly moving. If the pipeline harmony breaks down, the system stalls.

• RISC systems depend on special language programs called optimizing compilers that analyze the instruction steps they generate to see whether rearranging the instructions will better match the needs of the microprocessor pipeline. In effect, RISC programs are analyzed and rewritten for optimum speed before they are used. The extra time spent on preparing the program pays off in increased performance every time it runs. Commercial programs are already compiled when you get them, so you normally don't see the extra effort exerted by the optimizing compiler. You just get quicker results.

• Design simplicity. Above all, simplicity is the key to the design of a RISC machine or microprocessor. Although, for example, the Intel 80486 microprocessor has the equivalent of about one million transistors inside its package, the RISC-based MIPS M/2000 has only about 120,000; yet the two are comparable in performance. Fewer transistors mean fewer things to go wrong. RISC chips aren't necessarily more reliable, but making them without fabrication errors is easier than with more complex chips.

More important than number of transistors is the amount of space on the silicon chip that needs to be used to make a microprocessor. As the area of a chip increases, the likelihood of fabrication errors increases. During the fabrication process, errors are inevitable. A speck of dust or a bit of semiconductor that doesn't grow or etch properly can prevent the finished circuit from working. A number of such defects are inevitable on any single silicon matrix. The larger and more complex the circuits on the matrix, the more likely any one (or all) of them will be plagued by a defect. Consequently, the yield of usable circuits from a matrix plummets as the circuits become more complex and larger. Moreover, the bigger the design of a chip, the fewer patterns that will fit on a die. That is, the fewer chips that can be grown at a time with given fabrication equipment. Overall, the yield of RISC chips can thus be greater. In more practical terms, it costs more to build more complex microprocessors.

Because they are simpler, RISC chips are easier to design. Fewer transistors means less circuitry to lay out, test, and give engineers nightmares. Just as the blueprints of an igloo would be more manageable than those for a Gothic cathedral, a RISC chip design takes less work and can be readied faster.

Little wonder, then, why new microprocessor manufacturers favor RISC. In fact, some people claim that every microprocessor designed since 1985 has been RISC. Like every exaggeration, this one holds more than a grain of truth. RISC ideas have infiltrated every high performance microprocessor design. The only CISC chips surviving in the high performance market are those designed by Intel, and even the newest of them incorporate RISC concepts. RISC has become such a big selling point that every chip maker claims to have it. In that no one can pin down exactly what constitutes RISC, who is to say otherwise?

In light of all the advantages of RISC, the survival of any CISC microprocessors might seem odd. In truth, CISC chips in the real world outnumber RISC chips by a thousand to one or more. Fax machines, microwave ovens, hand held calculators, VCRs, even automobiles all have microprocessors inside, and such chips are almost universally CISC chips. The power and performance of RISC is simply unnecessary in such applications. Even in computers, CISC-based systems outsell RISC machines by a factor on the order of 20 to 1.