PCI Signal Groups

For purposes of definition, the PCI signals can be classified in several functional groups.

System

CLK Provides timing for all PCI transactions and is an input to every PCI device. All other PCI signals except RST# and INTA# through INTD# are sampled on the rising edge of CLK. (in) RST# Brings PCI-specific registers, sequencers, and signals to a consistent state. Whenever RST# is asserted, all PCI output signals must be driven to their benign state. In general, this means they must be tri-stated. (in)

Address and Data

AD[31::0] Address and data are multiplexed on the same set of pins. A PCI transaction consists of an address phase followed by one or more data phases. (t/s)

C/BE[3::0] Bus command and byte enables are multiplexed on the same pins. During the address phase of a transaction, C/BE[3::0] define a bus command. During each data phase, C/BE[3::0] are used as byte enables to determine which byte lanes carry valid data. C/BE[0] applies to byte 0 (lsb) and C/BE[3] applies to byte 3 (msb). (t/s) PAR Even Parity across AD[31::0] and C/BE[3::0]. All PCI agents are required to generate parity. (t/s)

Interface Control

FRAME# Driven by the current master to indicate the beginning and duration of a transaction. Data transfer continues while FRAME# is asserted. When FRAME# is de-asserted, the transaction is in its final data phase or has completed. (s/t/s)

IRDY# Initiator Ready indicates that the bus master is able to complete the current data phase. During a write, IRDY# indicates that valid data is present on AD[31::0]. During a read it indicates that the master is prepared to accept data. (s/t/s)

TRDY# Target Ready indicates that the selected target device is able to complete the current data phase. During a read, TRDY# indicates that valid data is present on AD[31::0]. During a write, it indicates that the target is prepared to accept data. A data phase completes on any clock cycle during which both IRDY# and TRDY# are asserted. (s/t/s)

STOP# Indicates that the selected target requests the master to terminate the current transaction. (s/t/s)

LOCK# Indicates an atomic operation that may require multiple transactions to complete. (s/t/s)

IDSEL Initialization Device Select is a chip select used during configuration transactions. (in)

DEVSEL# Device Select indicates that a device has decoded its address as the target of the current transaction. (s/t/s)

Arbitration

REQ# Request indicates to the central arbiter that an agent desires to use the bus. Every potential bus master has its own pointto- point REQ# signal. (t/s)

GNT# Grant indicates to an agent that is asserting its REQ# signal that access to the bus has been granted. Every potential bus master has its own point-to-point GNT# signal. (t/s)

Error Reporting

PERR# For reporting data Parity Errors during all PCI transactions except a Special Cycle. (s/t/s)

SERR# System Error is for reporting address parity errors, data parity errors on Special Cycle commands, and any other potentially catastrophic system error. (o/d)

Interrupt (optional)

INTA# through INTD# are used by a device to request attention from its device driver. A single-function device may only use INTA#. Multi-function devices may use any combination of INTx# signals. (o/d)

64-bit Bus Extension (optional)

AD[63::32] Upper 32 address and data bits. (t/s) C/BE[7::4] Upper byte enable signals. Generally not valid during address phase. (t/s)

REQ64# Request 64-bit Transfer indicates that the current bus master desires to execute a 64-bit transfer. (s/t/s)

ACK64# Acknowledge 64-bit Transfer indicates that the selected target is willing to execute 64-bit transfers. 64-bit transfers can only occur when both REQ64# and ACK64# are asserted. (s/t/s) PAR64 Even Parity over AD[63::32] and C/BE[7::4]. (t/s)

JTAG/Boundary Scan (optional)

The PCI specification reserves a set of pins for implementing a Test Access Port (TAP) conforming to IEEE Standard 1149.1, Test Access Port and Boundary Scan Architecture. This provides a reliable, well-defined mechanism for testing a device or board.

Additional Signals

These signals are not part of the basic PCI protocol but implement additional features that are useful in certain operating environments. PRSNT[1:2]# These are defined for add-in boards but not for motherboard devices. The Present signals indicate to the motherboard that a board is physically present and, if it is, its total power requirements.

Add-in boards are required to implement the Present signals but they are optional for motherboards.

CLKRUN# Clock Running is an optional input to a device to determine the state of CLK. It is output by a device that wishes to control the state of the clock. Assertion means the clock is running at its normal speed. De-assertion is a request to slow down or stop the clock. This is intended as a power saving mechanism in mobile environments and is described in the PCI Mobile Design Guide. The standard PCI connector does not have a pin for CLKRUN#. (in, o/d, s/t/s)

M66EN 66MHz_Enable indicates to a device that the bus segment is running at 66 MHz. (in)

PME# Power Management Event is an optional signal that allows a device to request a change in the device or system power state. The operation of this signal is described in the PCI Bus Power Management Interface Specification. (o/d)

3.3Vaux Auxiliary 3.3 volt Power allows an add-in card to generate power management events even when main power to the card is turned off. The operation of this signal is described in the PCI Bus Power Management Interface Specification. (in)