Industry Standard Architecture

By 1984, the rudimentary design of the PC bus was already falling behind the times. As IBM's engineers were working on a revolutionary new product (for then) based on a fast 286 microprocessor designed to run at 8 MHz (though initially limited to 6 MHz), they confronted a bus unsuited for the performance level of the new machine. Because the 286 used a full 16-bit data bus, IBM decided to add more data signals (as well as address and control signals) to the PC bus to match the capabilities of the new and more powerful chip. The bus speed of the AT also was matched to the microprocessor, so again no performance penalty was incurred in connecting a peripheral-even expansion memory-to the bus.

Not only was the PC bus limited in its memory handling and the width of its data path to the capabilities of a microprocessor on the road to oblivion (the 8088), but also many of the available system services were in too short supply for growth of the PC beyond a desktop platform for simple, single-minded jobs. For example, most systems ran out of hardware interrupts long before they ran out of expansion slots and expansion boards needing interrupts for control. At the same time, engineers were faced by the profusion of PC bus-based expansion products, many of those made by IBM, which would be rendered incompatible if the bus were radically changed. A complete redesign required creating an entirely new line of expansion products for IBM and the compatibles industry, probably creating an outcry loud enough to weaken the IBM standard.

As a result of balancing these conflicting needs, the new AT bus was born a hybrid. It retained compatibility with most earlier PC expansion products, while adding the functionality needed to push forward into full 16-bit technology. In addition, The AT bus contained a few new ideas (at least for PC-compatible computers) that hinted at-and perhaps even foretold-the Micro Channel. Inherent in the AT bus but almost entirely unused are provisions for cohabiting microprocessors inside the system, able to take control and share resources.

The big physical difference between the PC/XT bus and the AT bus was the addition of a second connector to carry more data and address lines-four more address lines and eight data-for a total of 16 data lines and 24 address lines, enough to handle 16 megabytes, the physical addressing limit of the 80286 chip. To make up for some of the shortcomings of the PC, which limited its expandability, the new AT bus also included several new interrupt and DMA control lines. In addition, IBM added a few novel connections. One in particular helps make expansion boards compatible across the 8- and 16-bit lines of the IBM PC; it signals to the host that the card in the socket uses the PC or AT bus.

Maintaining physical compatibility with the earlier PC bus was accomplished with the simple but masterful stroke of adding the required new bus connections on a supplementary connector rather than redesigning the already entrenched 62-pin connector. Expansion cards that only required an 8-bit interface and needed no access to protected mode memory locations or the advanced system services of the AT could be designed to be compatible with the full line of 8- and 16-bit IBM-standard computers. Those needing the speed or power of the AT could get it through the supplemental connector. The design even allowed cards to use either 8- or 16-bit expansion depending on the host in which they were installed.

Because of its initial speed and data-path match with the 286 microprocessor, the original AT bus substantially out-performed the PC bus-its 16-bit data path combined with its 8 MHz clock (in its most popular form) yielded a potential peak transfer rate of 8MB/sec. Its 24 address lines put 16MB of memory within reach. However, the number of useful I/O ports was still limited to 1,024 because of compatibility concerns with PC bus expansion boards.

The AT bus design incorporated one major structural difference over the original PC bus, however. Where the PC had a single oscillator to control all its timing signals including bus and microprocessor, the AT used several separate oscillators. The microprocessor speed, time-of-day clock, system timer, and bus speed were separated and could be independently altered. As a result, separate clocks could be used for the microprocessor and the expansion bus (as well as the system timers). This change allowed expansion boards to operate at a lower speed from that of the microprocessor. Because of this change, the ultra-compatible AT bus could be used with higher performance PCs as they became available. Although expansion boards might not work at the 25 MHz or 33 MHz clock speed of 386 and newer microprocessors, the bus could be held back to its 8 MHz rate (or a slightly higher sub-multiple of the microprocessor clock frequency) to ensure backward compatibility with old expansion boards. At first, the lower speed of the bus was no problem because nothing anyone wanted to plug into the bus needed to transfer data faster than 8MB/sec. For example, the fastest devices of the time-state-of-the-art ESDI drives-pushed data around at a 1.25MB/sec rate, well within the peak 8MB/sec limit of ISA. Eventually, however, the speed needs of peripherals (and memory) left the AT bus design far behind.

One glaring problem with the original PC and AT expansion buses was that they were designed not just for peripherals but also for the basic memory expansion of the host PC. This worked at first, when both microprocessor and bus ran at the same speed, but became bothersome as microprocessors raced ahead of bus capabilities-to such extreme rates as 16 MHz! Adding memory for a fast microprocessor into a slow bus just doesn't make sense. Every time the PC would need to access its bus-mounted memory, it would have to slow down to bus speed.

In early 1987, Compaq Computer Corporation cleverly sidestepped this problem with the introduction of its first Deskpro 386, which operated at 16 MHz. The first dual-bus PC, the Deskpro was the first machine to provide a separate bus for its memory, operating at microprocessor speed, and for input/output operations, operating at the lower speeds that expansion boards can tolerate. All modern PCs exploit this dual-bus concept, expanding on it with a third bus. The AT bus suffered another shortcoming. Although IBM documented the function of every pin on the AT bus, IBM never published a rigorous set of timing specifications for the signals on the bus. As a result, every manufacturer of AT expansion boards had to guess at timing and hope that their products would work in all systems. Although this empirical approach usually did not interfere with operation at 8 MHz, compatibility problems arose when some PC makers pushed the AT bus beyond that speed. The timing specifications of the AT bus were not officially defined until 1987 when a committee of the IEEE (Institute of Electrical and Electronic Engineers) formally approved a bus standard that became known as Industry Standard Architecture or simply ISA. It also goes under several other names: ISA, classic bus, and its original name, AT bus.

The problem with holding the speed of the ISA bus at 8 MHz for backward expansion board compatibility first became apparent when people wanted to add extra memory to their higher speed PCs. When the microprocessor clock speed exceeded the bus speed, the microprocessor had to slow down (by adding wait states) whenever it accessed memory connected through the expansion bus. System performance consequently suffered, sometimes severely.

System designers at Compaq solved the problem by devoting a special, second bus to memory in the company's 1987 Deskpro 386. All current ISA-based PCs follow this design-a separate bus for high speed memory and another for I/O expansion.

Since the time the IEEE set the ISA specification, its bus signals have remained essentially unchanged. The introduction of the Plug-and-Play ISA specification on May 28, 1993, a joint development by Intel and Microsoft, alters the way expansion boards work in conjunction with the bus.

Plug-and-Play ISA is designed to give ISA systems the same, if not better, self-configuration capabilities enjoyed by more recent expansion bus designs. In fully compliant systems, you can plug in any combination of expansion boards and never have to worry about such things as DIP switch settings, jumper positions, interrupts, DMA channels, ports, or ROM ranges. Each Plug-and-Play ISA card can tell its computer host exactly what resource it requires. If the resource requests of two or more cards conflict, the Plug-and-Play system automatically straightens things out.

Instead of altering the bus, Plug-and-Play ISA substitutes an elaborate software-based isolation protocol. Effectively, it keeps an expansion board switched off until it can be uniquely addressed, so that one card can be queried at a time. The host system then can determine the resources the board needs; check to make sure that no other board requires the same resources; and reserve those resources for the target board.

Although Plug-and-Play ISA does not require them, it can make use of slot-specific address-enabled signals. The use of such signals-which are now not part of the ISA specification-can eliminate the complex software-query system used for isolating cards. While software-based Plug-and-Play configuration is possible with current systems, using the streamlined hardware-based scheme requires new motherboards.