Enhanced ISA

In 1988, to frustrate the perceived attempt by IBM at hegemony over the PC industry, a consortium of nine companies (termed by industry wags as the "Gang of Nine") made up of AST Research, Compaq Computer Corp., Epson, Hewlett-Packard, NEC, Olivetti, Tandy, Wyse, and Zenith Data Systems developed Extended Industry Standard Architecture, more commonly known as EISA. Compaq led the effort, but passed control and management of the standard to an independent organization, BCPR Services, which now officiates the standard.

The basic design of EISA amounts to the features of Micro Channel implemented in technologies free from IBM's control. Although the exciting new bus standard certainly incorporates some original and clever thoughts, EISA really amounts to the greatest hits of computer buses-the best ideas drawn from other bus designs and the whole computer industry.

That description is not meant to be derogatory any more than it is accidental that EISA is so derivative. From its very beginnings, EISA was avowedly designed not as an original concept but as an enhancement to the familiar AT bus. The reality of EISA goes far beyond merely specifying how to add 16 new data lines to the classic AT bus. By borrowing the best ideas from other bus designs-features such as bus mastering, automated setup, and interrupt sharing-then mixing in its own new data transfer modes, EISA has become a powerful and useful expansion design.

Of course, one contrary viewpoint is to label EISA the computer equivalent of a camel-rather than a horse-drawn by committee, a standard so executed by the Gang of Nine. The goal, announced September 13, 1988, was to design a 32-bit successor to Industry Standard Architecture-one that remained compatible to it instead of replacing it.

To improve performance, EISA relied on four advanced transfer modes that trim the number of clock cycles needed to move each byte. The most efficient mode compresses a transfer cycle into a single clock tick, putting the address cycle on the rising edge and data cycle on the falling edge of a single clock pulse. With its 32-bit bus width, a nominal 8.33 MHz clock speed carried over for compatibility with ISA, and its advanced transfer modes, EISA can reach a peak transfer rate of 33MB/sec.

At more than 50 percent faster, EISA was designed to make Micro Channel look second rate. IBM's response was to add new modes to Micro Channel to allow higher throughput and increase data integrity. The revised Micro Channel specification optionally includes a Streaming Data Mode, which doubles burst speed. A block transfer begins by putting a starting address on the address bus. Thereafter, the entire block moves at a one transfer-per-clock cycle rate.

Because the address bus is not used during these data streams, IBM allowed for it to serve as an auxiliary data channel, effectively broadening the data bus to 64 bits during bursts and again doubling the transfer rate. Together these new modes quadrupled the Micro Channel transfer rate to 80MB/sec.

Another new Micro Channel option allowed doubling the bus clock rate to 20 MHz while accommodating 10 MHz boards. This pushes the bus to a potential peak transfer rate of 160MB/sec. Note, however, all these advanced features are optional, and no existing PC uses the complete package.

Faced with technology outrunning their bus, the EISA consortium has gone back to work and is now developing an EISA-2 specification. Coupling EISA existing advanced transfer modes with the streaming data and multiplexed transfer concepts borrowed from Micro Channel, EISA-2 promises a potential transfer rate of 132MB/sec.